Complementary Metal Oxide Silicon (CMOS) technology has played an increasingly important role in the integrated circuit (IC) industry. Over the years, the technology has improved to the point that CMOS technology clearly holds center stage as the dominant VLSI technology. CMOS VLSI technology provides a large number of transistors and input/output (I/O) interfaces on an IC, sometimes called a chip, with extremely high operating speed. These advances in CMOS VLSI technology and especially in fabrication and manufacturing technologies have been driven by the reduction and downsizing of device dimensions.
A number of enhancements may be added to the CMOS processes, primarily to increase routability of circuits, provide high quality capacitors for analog circuits and memories, or provide resistors of variable characteristics. Such enhancements includes providing two or more metal layers or double or triple polycrystalline layers. Notably, present technology provides seven or more layers of metal which can be used as signal and power-routing layers. These additional layers ease the routing of signals between modules and improves the power and clock distributions to modules. Improved routability is achieved through additional layers of metal or by improving the existing polysilicon interconnection layer.
In CMOS technology, three types of interconnects are used: diffusion, polysilicon and metal. Ten years ago a second metal layer became very important in CMOS design. The use of seven or more metal layers provides even more improvements over two layers. Aluminum (Al) and copper (Cu) as well as other metals and alloys known in the art can be used as interconnect metals. If some form of planarization is employed, other metal layer pitches can be the same as the first. As the vertical topology becomes more varied, the width and spacing of metal conductors has increased such that the conductors resist thinning and breaking between vertical topologies.
Contacting a first metal layer to a second or higher level metal layer is achieved by a via. When a further contact to diffusion or polysilicon is required, a separation between the via and the contact cut may be required. To do so, a first level metal tab is used to bridge between the second layer metal and the first layer metal. Processes typically require metal borders around a via on both levels of connection to metal layers. These metal borders assure proper connection to the metal layer and avoid potential intermittent contacts.
Most ICs with a large number of transistors and extremely high operating speed with a large count of I/O signal interfaces are subject to core power supply voltage IR drops, if they are not handled and measured properly. Note here that “I” corresponds to current and “R” corresponds to resistance. A product of I and R yields the resulting voltage drop associated with the current and resistance. The term IR is used in the art, however, as it draws a designer to consider in the mind of considering both current and resistance effects in reducing supply voltages in an IC. The downsizing of device dimensions results in increased performance, reduced cost and increased life cycle. However, such downsizing makes IR drops even more of a concern as it is critical that power to the IC is maintained stable and within a very narrow range. In a typical IC situation, the number of I/O interfaces is fixed the power consumption and heat generation increases due to the increased functionality and its associated increase in transistors. Moreover, undesirable IR drops become even more serious in low-voltage supply applications. For example, where an IC is operating at 1.8 volts, even a small IR drop can cause the IC to fail. Then, even a noisy power supply can cause the IC to fail for such a low operating voltage.